module uart_byte_rx_test(
	Clk,
	Rst_n,
	uart_rx,
	// TFT
	TFT_RGB,
	TFT_HS,
	TFT_VS,
	TFT_CLK,
	TFT_DE,
	TFT_PWM
);
	input Clk;
	input Rst_n;
	input uart_rx;
	
	// tft output
	output TFT_HS;
	output TFT_VS;
	output TFT_CLK;
	output TFT_DE;
	output TFT_PWM;
	output [15:0]TFT_RGB;
	
	
	wire [8:0] rx_data;
	wire rx_done;
	reg [1:0] bps_setting;
	reg [1:0] check_setting;
	
	
	// tft ram
	reg ram_wren;
	reg [11:0]ram_wraddress;
	
	uart_byte_rx uart_byte_rx_instance0(
		.clk(Clk),			   // 时钟发生器：system 50MHz
		.rst_n(Rst_n), 			// 复位使能：reg
		.uart_rx(uart_rx),		   // 串口接受线: system
		.bps_setting(bps_setting), 	// 波特率：reg 
		.check_setting(check_setting), // 校验方式: reg
		.data(rx_data),			   // 数据: reg
		.rx_done(rx_done)   		// 一次接收数据完成标志
	);
	
	vision_ctrl vision_ctrl_instance0(
		.Clk(Clk),
		.Rst_n(Rst_n),
		.TFT_RGB(TFT_RGB),//TFT数据输出
		.TFT_HS(TFT_HS),	//TFT行同步信号
		.TFT_VS(TFT_VS),	//TFT场同步信号
		.TFT_CLK(TFT_CLK),
		.TFT_DE(TFT_DE),
		.TFT_PWM(TFT_PWM),
		// RAM 写
		.ram_wren(ram_wren),
		.ram_wraddress(ram_wraddress),
		.ram_input(rx_data)
	);
	
	always @(posedge Clk)
	begin
		bps_setting <= 2'b00;
		check_setting <= 2'b00;
	end
	
	always @(posedge Clk or negedge Rst_n)
	begin
		if (!Rst_n)
			ram_wraddress <= 12'd81;
		else
			begin
				if (ram_wraddress == 2159)
							ram_wraddress <= 12'd81;
				else if ((ram_wraddress + 1) % 80 == 0)
					begin 
						ram_wraddress <= ram_wraddress + 2;
					end
				else if (ram_wraddress % 80 == 0)
					begin 
						ram_wraddress <= ram_wraddress + 1;
					end
				else 
					ram_wraddress <= ram_wraddress;
			
				if (rx_done == 1)
				begin 
					ram_wren <= 1'b1;
				end
				
				if (ram_wren == 1)
				begin 
					ram_wren <= 1'b0;
					ram_wraddress <= ram_wraddress + 1; 
				end
			end
	end
	
endmodule
